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1.0.4 update

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Dolu1990
2017-12-20 15:00:48 +01:00
parent bb1a2d1b9f
commit d4d59c7cc1
2 changed files with 2 additions and 4 deletions
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src/main/scala/mylib/MyTopLevelSim.scala
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@@ -13,8 +13,6 @@ object MyTopLevelSim {
SimConfig(new MyTopLevel).withWave.doManagedSim{dut =>
//Fork a process to generate the reset and the clock on the dut
dut.clockDomain.disassertReset() //Verilator sim fix, will be fixed in SpinalHDL 1.0.4
sleep(0)
dut.clockDomain.forkStimulus(period = 10)