From d4d59c7cc1ca2f23b18d2e350320a5031c696a10 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Wed, 20 Dec 2017 15:00:48 +0100 Subject: [PATCH] 1.0.4 update --- build.sbt | 4 ++-- src/main/scala/mylib/MyTopLevelSim.scala | 2 -- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/build.sbt b/build.sbt index 6790247..b4b6321 100644 --- a/build.sbt +++ b/build.sbt @@ -7,8 +7,8 @@ scalaVersion := "2.11.6" EclipseKeys.withSource := true libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.3", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.3" + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.4", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.4" ) addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") diff --git a/src/main/scala/mylib/MyTopLevelSim.scala b/src/main/scala/mylib/MyTopLevelSim.scala index 2de9ac8..dac5b49 100644 --- a/src/main/scala/mylib/MyTopLevelSim.scala +++ b/src/main/scala/mylib/MyTopLevelSim.scala @@ -13,8 +13,6 @@ object MyTopLevelSim { SimConfig(new MyTopLevel).withWave.doManagedSim{dut => //Fork a process to generate the reset and the clock on the dut - dut.clockDomain.disassertReset() //Verilator sim fix, will be fixed in SpinalHDL 1.0.4 - sleep(0) dut.clockDomain.forkStimulus(period = 10)