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Update to SpinalHDL 1.0.3

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Dolu1990
2017-12-20 00:08:40 +01:00
parent 43c46edec8
commit bb1a2d1b9f
2 changed files with 6 additions and 4 deletions
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6
build.sbt
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@@ -1,4 +1,4 @@
name := "SpinalBaseProject" name := "SpinalTemplateSbt"
version := "1.0" version := "1.0"
@@ -7,8 +7,8 @@ scalaVersion := "2.11.6"
EclipseKeys.withSource := true EclipseKeys.withSource := true
libraryDependencies ++= Seq( libraryDependencies ++= Seq(
"com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.2", "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.3",
"com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.2" "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.3"
) )
addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2") addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")

4
src/main/scala/mylib/MyTopLevelSim.scala
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@@ -13,6 +13,8 @@ object MyTopLevelSim {
SimConfig(new MyTopLevel).withWave.doManagedSim{dut => SimConfig(new MyTopLevel).withWave.doManagedSim{dut =>
//Fork a process to generate the reset and the clock on the dut //Fork a process to generate the reset and the clock on the dut
dut.clockDomain.disassertReset() //Verilator sim fix, will be fixed in SpinalHDL 1.0.4
sleep(0)
dut.clockDomain.forkStimulus(period = 10) dut.clockDomain.forkStimulus(period = 10)
@@ -30,10 +32,10 @@ object MyTopLevelSim {
dut.clockDomain.waitRisingEdge() dut.clockDomain.waitRisingEdge()
//Update the reference model values //Update the reference model values
val modelFlag = modelState == 0 || cond1
if(cond0) { if(cond0) {
modelState = (modelState + 1) & 0xFF modelState = (modelState + 1) & 0xFF
} }
val modelFlag = modelState == 0 || cond1
//Check that the dut values match with the reference model ones //Check that the dut values match with the reference model ones
assert(dut.io.state.toInt == modelState) assert(dut.io.state.toInt == modelState)