diff --git a/build.sbt b/build.sbt
index ede7668..6790247 100644
--- a/build.sbt
+++ b/build.sbt
@@ -1,4 +1,4 @@
-name := "SpinalBaseProject"
+name := "SpinalTemplateSbt"
 
 version := "1.0"
 
@@ -7,8 +7,8 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.2",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.2"
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.3",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.3"
 )
 
 addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
diff --git a/src/main/scala/mylib/MyTopLevelSim.scala b/src/main/scala/mylib/MyTopLevelSim.scala
index 277fa10..2de9ac8 100644
--- a/src/main/scala/mylib/MyTopLevelSim.scala
+++ b/src/main/scala/mylib/MyTopLevelSim.scala
@@ -13,6 +13,8 @@ object MyTopLevelSim {
     SimConfig(new MyTopLevel).withWave.doManagedSim{dut =>
 
       //Fork a process to generate the reset and the clock on the dut
+      dut.clockDomain.disassertReset()  //Verilator sim fix, will be fixed in SpinalHDL 1.0.4
+      sleep(0)
       dut.clockDomain.forkStimulus(period = 10)
 
 
@@ -30,10 +32,10 @@ object MyTopLevelSim {
         dut.clockDomain.waitRisingEdge()
 
         //Update the reference model values
-        val modelFlag = modelState == 0 || cond1
         if(cond0) {
           modelState = (modelState + 1) & 0xFF
         }
+        val modelFlag = modelState == 0 || cond1
 
         //Check that the dut values match with the reference model ones
         assert(dut.io.state.toInt == modelState)