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Update Config.scala

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onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim
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Dolu1990
2025-04-06 14:58:20 +02:00
committed by GitHub
parent 2aefabbbad
commit 976ceca3a3
1 changed files with 1 additions and 1 deletions
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hw/spinal/projectname/Config.scala
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@@ -9,7 +9,7 @@ object Config {
defaultConfigForClockDomains = ClockDomainConfig( defaultConfigForClockDomains = ClockDomainConfig(
resetActiveLevel = HIGH resetActiveLevel = HIGH
), ),
onlyStdLogicVectorAtTopLevelIo = true onlyStdLogicVectorAtTopLevelIo = false
) )
def sim = SimConfig.withConfig(spinal).withFstWave def sim = SimConfig.withConfig(spinal).withFstWave