Files
SpinalTemplateSbt/hw/spinal/projectname/Config.scala
Dolu1990 976ceca3a3 Update Config.scala
onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim
2025-04-06 14:58:20 +02:00

17 lines
339 B
Scala

package projectname
import spinal.core._
import spinal.core.sim._
object Config {
def spinal = SpinalConfig(
targetDirectory = "hw/gen",
defaultConfigForClockDomains = ClockDomainConfig(
resetActiveLevel = HIGH
),
onlyStdLogicVectorAtTopLevelIo = false
)
def sim = SimConfig.withConfig(spinal).withFstWave
}