From 976ceca3a31ebc0805f978eb08af749b575c9060 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sun, 6 Apr 2025 14:58:20 +0200
Subject: [PATCH] Update Config.scala

onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim
---
 hw/spinal/projectname/Config.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/spinal/projectname/Config.scala b/hw/spinal/projectname/Config.scala
index f3a2e3e..433ff2e 100644
--- a/hw/spinal/projectname/Config.scala
+++ b/hw/spinal/projectname/Config.scala
@@ -9,7 +9,7 @@ object Config {
     defaultConfigForClockDomains = ClockDomainConfig(
       resetActiveLevel = HIGH
     ),
-    onlyStdLogicVectorAtTopLevelIo = true
+    onlyStdLogicVectorAtTopLevelIo = false
   )
 
   def sim = SimConfig.withConfig(spinal).withFstWave