Clearning + Verilog

MyTopLevel.v

@@ -0,0 +1,33 @@
+
+module MyTopLevel
+(
+  input  io_cond0,
+  input  io_cond1,
+  output  io_flag,
+  output [7:0] io_state,
+  input  clk,
+  input  reset 
+);
+
+  reg [7:0] counter;
+  wire [7:0] zz_1;
+  wire  zz_2;
+  wire  zz_3;
+  assign io_flag = zz_3;
+  assign io_state = counter;
+  assign zz_1 = (counter + (8'b00000001));
+  assign zz_2 = (counter == (8'b00000000));
+  assign zz_3 = (zz_2 || io_cond1);
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset) begin
+      counter <= (8'b00000000);
+    end else begin
+      if(io_cond0)begin
+        counter <= zz_1;
+      end
+    end
+  end
+
+endmodule
+

src/main/scala/MyCode/TopLevel.scala

@@ -26,9 +26,9 @@ class MyTopLevel extends Component {
     val cond0 = in  Bool
     val cond1 = in  Bool
     val flag  = out Bool
-    val state = out UInt(8 bit)
+    val state = out UInt(8 bits)
   }
-  val counter = Reg(UInt(8 bit)) init(0)
+  val counter = Reg(UInt(8 bits)) init(0)
 
   when(io.cond0){
     counter := counter + 1
@@ -41,6 +41,7 @@ class MyTopLevel extends Component {
 object MyTopLevel {
   def main(args: Array[String]) {
     SpinalVhdl(new MyTopLevel)
+    //SpinalVerilog(new MyTopLevel)
   }
 }