diff --git a/MyTopLevel.v b/MyTopLevel.v
new file mode 100644
index 0000000..b781bfe
--- /dev/null
+++ b/MyTopLevel.v
@@ -0,0 +1,33 @@
+
+module MyTopLevel
+(
+  input  io_cond0,
+  input  io_cond1,
+  output  io_flag,
+  output [7:0] io_state,
+  input  clk,
+  input  reset 
+);
+
+  reg [7:0] counter;
+  wire [7:0] zz_1;
+  wire  zz_2;
+  wire  zz_3;
+  assign io_flag = zz_3;
+  assign io_state = counter;
+  assign zz_1 = (counter + (8'b00000001));
+  assign zz_2 = (counter == (8'b00000000));
+  assign zz_3 = (zz_2 || io_cond1);
+  always @ (posedge clk or posedge reset)
+  begin
+    if (reset) begin
+      counter <= (8'b00000000);
+    end else begin
+      if(io_cond0)begin
+        counter <= zz_1;
+      end
+    end
+  end
+
+endmodule
+
diff --git a/src/main/scala/MyCode/TopLevel.scala b/src/main/scala/MyCode/TopLevel.scala
index 852512d..5a1ba7a 100644
--- a/src/main/scala/MyCode/TopLevel.scala
+++ b/src/main/scala/MyCode/TopLevel.scala
@@ -23,24 +23,25 @@ import spinal.lib._
 
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in Bool
-    val cond1 = in Bool
-    val flag = out Bool
-    val state = out UInt(8 bit)
+    val cond0 = in  Bool
+    val cond1 = in  Bool
+    val flag  = out Bool
+    val state = out UInt(8 bits)
   }
-  val counter = Reg(UInt(8 bit)) init(0)
+  val counter = Reg(UInt(8 bits)) init(0)
 
   when(io.cond0){
     counter := counter + 1
   }
 
   io.state := counter
-  io.flag := (counter === 0) | io.cond1
+  io.flag  := (counter === 0) | io.cond1
 }
 
 object MyTopLevel {
   def main(args: Array[String]) {
     SpinalVhdl(new MyTopLevel)
+    //SpinalVerilog(new MyTopLevel)
   }
 }