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34 lines
589 B
Verilog
34 lines
589 B
Verilog
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module MyTopLevel
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(
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input io_cond0,
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input io_cond1,
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output io_flag,
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output [7:0] io_state,
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input clk,
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input reset
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);
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reg [7:0] counter;
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wire [7:0] zz_1;
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wire zz_2;
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wire zz_3;
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assign io_flag = zz_3;
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assign io_state = counter;
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assign zz_1 = (counter + (8'b00000001));
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assign zz_2 = (counter == (8'b00000000));
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assign zz_3 = (zz_2 || io_cond1);
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always @ (posedge clk or posedge reset)
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begin
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if (reset) begin
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counter <= (8'b00000000);
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end else begin
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if(io_cond0)begin
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counter <= zz_1;
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end
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end
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end
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endmodule
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