1 Commits

Author SHA1 Message Date
Dolu1990
0340f9799c Add test folder 2023-12-11 12:16:37 +01:00
7 changed files with 8 additions and 8 deletions

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@@ -1 +1 @@
0.11.11
0.9.8

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@@ -1,16 +1,16 @@
ThisBuild / version := "1.0"
ThisBuild / scalaVersion := "2.13.14"
ThisBuild / scalaVersion := "2.12.18"
ThisBuild / organization := "org.example"
val spinalVersion = "1.12.3"
val spinalVersion = "1.9.4"
val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
lazy val projectname = (project in file("."))
.settings(
name := "myproject",
Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
Test / scalaSource := baseDirectory.value / "test" / "spinal",
libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
)

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@@ -1,9 +1,9 @@
import mill._, scalalib._
val spinalVersion = "1.12.3"
val spinalVersion = "1.9.0"
object projectname extends SbtModule {
def scalaVersion = "2.13.14"
def scalaVersion = "2.12.16"
override def millSourcePath = os.pwd
def sources = T.sources(
millSourcePath / "hw" / "spinal"

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@@ -9,7 +9,7 @@ object Config {
defaultConfigForClockDomains = ClockDomainConfig(
resetActiveLevel = HIGH
),
onlyStdLogicVectorAtTopLevelIo = false
onlyStdLogicVectorAtTopLevelIo = true
)
def sim = SimConfig.withConfig(spinal).withFstWave

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@@ -1 +1 @@
sbt.version=1.10.2
sbt.version=1.6.0