SpinalHDL 1.12.3

onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim

.mill-version

@@ -1 +1 @@
-0.9.8
+0.11.11

build.sbt

@@ -2,13 +2,14 @@ ThisBuild / version := "1.0"
 ThisBuild / scalaVersion := "2.13.14"
 ThisBuild / organization := "org.example"
 
-val spinalVersion = "1.10.2a"
+val spinalVersion = "1.12.3"
 val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
 val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
 val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
 
 lazy val projectname = (project in file("."))
   .settings(
+    name := "myproject", 
     Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
     libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
   )

build.sc

@@ -1,6 +1,6 @@
 import mill._, scalalib._
 
-val spinalVersion = "1.10.2a"
+val spinalVersion = "1.12.3"
 
 object projectname extends SbtModule {
   def scalaVersion = "2.13.14"

hw/spinal/projectname/Config.scala

@@ -9,7 +9,7 @@ object Config {
     defaultConfigForClockDomains = ClockDomainConfig(
       resetActiveLevel = HIGH
     ),
-    onlyStdLogicVectorAtTopLevelIo = true
+    onlyStdLogicVectorAtTopLevelIo = false
   )
 
   def sim = SimConfig.withConfig(spinal).withFstWave

project/build.properties

@@ -1 +1 @@
-sbt.version=1.6.0
+sbt.version=1.10.2