Merge pull request #21 from numero-744/big-update

Big update

.gitignore

@@ -11,15 +11,21 @@ target
 lib_managed/
 src_managed/
 project/boot/
+project/project
 project/plugins/project/
 
 # Scala-IDE specific
 .scala_dependencies
 .worksheet
+.bloop
 
 .idea
 out
 
+# Metals
+.metals
+project/metals.sbt
+
 # Eclipse
 bin/
 .classpath
@@ -38,3 +44,4 @@ bin/
 
 simWorkspace/
 tmp/
+null

.mill-version

@@ -0,0 +1 @@
+0.9.8

.scalafmt.conf

@@ -0,0 +1,5 @@
+version = 3.6.0
+runner.dialect = scala212
+align.preset = some
+maxColumn = 120
+docstrings.wrap = no

README.md

@@ -21,8 +21,9 @@ sudo update-alternatives --config javac
 You need to install SBT
 
 ```sh
-echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
-sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
+echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
+echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
+curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
 sudo apt-get update
 sudo apt-get install sbt
 ```
@@ -36,7 +37,7 @@ unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
 unset VERILATOR_ROOT  # For bash
 cd verilator
 git pull        # Make sure we're up-to-date
-git checkout verilator_3_916
+git checkout v4.040
 autoconf        # Create ./configure script
 ./configure
 make -j$(nproc)
@@ -89,6 +90,8 @@ Normally, this must generate an MyTopLevel.v output files.
 
 ## Basics, with Eclipse and its scala plugin
 
+First, i "strongly" suggest to use intellij idea instead.
+
 You need to install :
 
 - Java JDK
@@ -100,9 +103,38 @@ You need to install :
 And do the following :
 
 - Clone or download this repository.
+- Revert changes from https://github.com/SpinalHDL/SpinalTemplateSbt/commit/173bbb9bb8cbf70087339104f6ebced9321908dd
 - Run ```sbt eclipse``` in the ```SpinalTemplateSbt``` directory.
 - Import the eclipse project from eclipse.
 - In the project (eclipse project GUI), right click on src/main/scala/mylib/MyTopLevel.scala, right click on MyTopLevelVerilog, and select run it
 
 Normally, this must generate output file ```MyTopLevel.v```.
 
+## Mill Support (Experimental)
+
+This Spinal Base Project contains support for the [Mill build tool](https://com-lihaoyi.github.io/mill).
+
+The prerequisites are the same as for using SBT, except for sbt itself. Additionally, the ```mill``` executable needs to be installed on the path. Download it to ```/usr/local/bin/mill``` or ```~/bin/mill``` according to the [installation instructions](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation).
+
+You can clone and use this repository in the following way.
+
+```sh
+git clone https://github.com/SpinalHDL/SpinalTemplateSbt.git
+```
+
+Open a terminal in the root of it and execute your favorite mill command. At the first execution, the process could take some seconds
+
+```sh
+cd SpinalTemplateSbt
+
+//If you want to generate the Verilog of your design
+mill mylib.runMain mylib.MyTopLevelVerilog
+
+//If you want to generate the VHDL of your design
+mill mylib.runMain mylib.MyTopLevelVhdl
+
+//If you want to run the scala written testbench
+mill mylib.runMain mylib.MyTopLevelSim
+```
+
+The top level spinal code is defined into src\main\scala\mylib

build.sbt

@@ -1,15 +1,16 @@
-name := "SpinalTemplateSbt"
+ThisBuild / version := "1.0"
+ThisBuild / scalaVersion := "2.12.16"
+ThisBuild / organization := "org.example"
 
-version := "1.0"
+val spinalVersion = "1.7.3"
+val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
+val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
+val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
 
-scalaVersion := "2.11.12"
-
-EclipseKeys.withSource := true
-
-libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.4.0",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.4.0",
-  compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % "1.4.0")
+lazy val mylib = (project in file("."))
+  .settings(
+    name := "SpinalTemplateSbt",
+    libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
   )
 
 fork := true

build.sc

@@ -0,0 +1,13 @@
+import mill._, scalalib._
+
+val spinalVersion = "1.7.3"
+
+object mylib extends SbtModule {
+  def scalaVersion = "2.12.14"
+  override def millSourcePath = os.pwd
+  def ivyDeps = Agg(
+    ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion",
+    ivy"com.github.spinalhdl::spinalhdl-lib:$spinalVersion"
+  )
+  def scalacPluginIvyDeps = Agg(ivy"com.github.spinalhdl::spinalhdl-idsl-plugin:$spinalVersion")
+}

project/build.properties

@@ -1 +1 @@
-sbt.version=1.2.7
+sbt.version=1.6.0

project/plugins.sbt

@@ -1,2 +1 @@
-addSbtPlugin("com.typesafe.sbteclipse" % "sbteclipse-plugin" % "5.2.4")
-
+addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.6")

src/main/scala/mylib/MyTopLevel.scala

@@ -1,37 +1,17 @@
-/*
- * SpinalHDL
- * Copyright (c) Dolu, All rights reserved.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 3.0 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library.
- */
-
 package mylib
 
 import spinal.core._
-import spinal.lib._
-
-import scala.util.Random
 
 // Hardware definition
-class MyTopLevel extends Component {
+case class MyTopLevel() extends Component {
   val io = new Bundle {
-    val cond0 = in  Bool
-    val cond1 = in  Bool
-    val flag  = out Bool
+    val cond0 = in  Bool()
+    val cond1 = in  Bool()
+    val flag  = out Bool()
     val state = out UInt(8 bits)
   }
-  val counter = Reg(UInt(8 bits)) init(0)
+
+  val counter = Reg(UInt(8 bits)) init 0
 
   when(io.cond0) {
     counter := counter + 1
@@ -40,28 +20,3 @@ class MyTopLevel extends Component {
   io.state := counter
   io.flag := (counter === 0) | io.cond1
 }
-
-//Generate the MyTopLevel's Verilog
-object MyTopLevelVerilog {
-  def main(args: Array[String]) {
-    SpinalVerilog(new MyTopLevel)
-  }
-}
-
-//Generate the MyTopLevel's VHDL
-object MyTopLevelVhdl {
-  def main(args: Array[String]) {
-    SpinalVhdl(new MyTopLevel)
-  }
-}
-
-
-//Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere
-object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC))
-
-//Generate the MyTopLevel's Verilog using the above custom configuration.
-object MyTopLevelVerilogWithCustomConfig {
-  def main(args: Array[String]) {
-    MySpinalConfig.generateVerilog(new MyTopLevel)
-  }
-}

src/main/scala/mylib/MyTopLevelFormal.scala

@@ -0,0 +1,24 @@
+package mylib
+
+import spinal.core._
+import spinal.core.formal._
+
+// You need SymbiYosys to be installed.
+// See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
+object MyTopLevelFormal extends App {
+  FormalConfig
+    .withBMC(10)
+    .doVerify(new Component {
+      val dut = FormalDut(MyTopLevel())
+
+      // Ensure the formal test start with a reset
+      assumeInitial(clockDomain.isResetActive)
+
+      // Provide some stimulus
+      anyseq(dut.io.cond0)
+      anyseq(dut.io.cond1)
+
+      // Check the state initial value and increment
+      assert(dut.io.state === past(dut.io.state + U(dut.io.cond0)).init(0))
+    })
+}

src/main/scala/mylib/MyTopLevelGen.scala

@@ -0,0 +1,25 @@
+package mylib
+
+import spinal.core._
+
+object MyTopLevelVerilog extends App {
+  // Generate the MyTopLevel's Verilog
+  SpinalVerilog(MyTopLevel())
+}
+
+object MyTopLevelVhdl extends App {
+  // Generate the MyTopLevel's VHDL
+  SpinalVhdl(MyTopLevel())
+}
+
+// Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one
+// This configuration can be resued everywhere
+object MySpinalConfig
+    extends SpinalConfig(
+      defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC)
+    )
+
+object MyTopLevelVerilogWithCustomConfig extends App {
+  // Generate the MyTopLevel's Verilog using the above custom configuration.
+  MySpinalConfig.generateVerilog(MyTopLevel())
+}

src/main/scala/mylib/MyTopLevelSim.scala

@@ -1,24 +1,18 @@
 package mylib
 
 import spinal.core._
-import spinal.sim._
 import spinal.core.sim._
 
-import scala.util.Random
-
-
-//MyTopLevel's testbench
-object MyTopLevelSim {
-  def main(args: Array[String]) {
-    SimConfig.withWave.doSim(new MyTopLevel){dut =>
+object MyTopLevelSim extends App {
+  SimConfig.withWave.doSim(MyTopLevel()) { dut =>
     // Fork a process to generate the reset and the clock on the dut
     dut.clockDomain.forkStimulus(period = 10)
 
     var modelState = 0
     for (idx <- 0 to 99) {
       // Drive the dut inputs with random values
-        dut.io.cond0 #= Random.nextBoolean()
-        dut.io.cond1 #= Random.nextBoolean()
+      dut.io.cond0.randomize()
+      dut.io.cond1.randomize()
 
       // Wait a rising edge on the clock
       dut.clockDomain.waitRisingEdge()
@@ -30,8 +24,7 @@ object MyTopLevelSim {
 
       // Update the reference model value
       if (dut.io.cond0.toBoolean) {
-          modelState = (modelState + 1) & 0xFF
-        }
+        modelState = (modelState + 1) & 0xff
       }
     }
   }