Merge pull request #11 from name1e5s/master

SpinalHDL 1.6.0

build.sbt

@@ -2,7 +2,7 @@ ThisBuild / version := "1.0"
 ThisBuild / scalaVersion := "2.11.12"
 ThisBuild / organization := "org.example"
 
-val spinalVersion = "1.5.0"
+val spinalVersion = "1.6.0"
 val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
 val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
 val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)

build.sc

@@ -1,6 +1,6 @@
 import mill._, scalalib._
 
-val spinalVersion = "1.5.0"
+val spinalVersion = "1.6.0"
 
 object mylib extends SbtModule {
   def scalaVersion = "2.12.14"

src/main/scala/mylib/MyTopLevel.scala

@@ -26,9 +26,9 @@ import scala.util.Random
 //Hardware definition
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in  Bool
-    val cond1 = in  Bool
-    val flag  = out Bool
+    val cond0 = in  Bool()
+    val cond1 = in  Bool()
+    val flag  = out Bool()
     val state = out UInt(8 bits)
   }
   val counter = Reg(UInt(8 bits)) init(0)