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new MyTopLevel -> MyTopLevel()

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This commit is contained in:
Côme ALLART
2022-11-18 00:37:28 +01:00
parent d40940a924
commit bbbac09f8f
3 changed files with 5 additions and 5 deletions
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2
src/main/scala/mylib/MyTopLevelFormal.scala
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@@ -9,7 +9,7 @@ object MyTopLevelFormal extends App {
FormalConfig FormalConfig
.withBMC(10) .withBMC(10)
.doVerify(new Component { .doVerify(new Component {
val dut = FormalDut(new MyTopLevel) val dut = FormalDut(MyTopLevel())
// Ensure the formal test start with a reset // Ensure the formal test start with a reset
assumeInitial(clockDomain.isResetActive) assumeInitial(clockDomain.isResetActive)

6
src/main/scala/mylib/MyTopLevelGen.scala
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@@ -4,12 +4,12 @@ import spinal.core._
object MyTopLevelVerilog extends App { object MyTopLevelVerilog extends App {
// Generate the MyTopLevel's Verilog // Generate the MyTopLevel's Verilog
SpinalVerilog(new MyTopLevel) SpinalVerilog(MyTopLevel())
} }
object MyTopLevelVhdl extends App { object MyTopLevelVhdl extends App {
// Generate the MyTopLevel's VHDL // Generate the MyTopLevel's VHDL
SpinalVhdl(new MyTopLevel) SpinalVhdl(MyTopLevel())
} }
// Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one // Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one
@@ -21,5 +21,5 @@ object MySpinalConfig
object MyTopLevelVerilogWithCustomConfig extends App { object MyTopLevelVerilogWithCustomConfig extends App {
// Generate the MyTopLevel's Verilog using the above custom configuration. // Generate the MyTopLevel's Verilog using the above custom configuration.
MySpinalConfig.generateVerilog(new MyTopLevel) MySpinalConfig.generateVerilog(MyTopLevel())
} }

2
src/main/scala/mylib/MyTopLevelSim.scala
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@@ -4,7 +4,7 @@ import spinal.core._
import spinal.core.sim._ import spinal.core.sim._
object MyTopLevelSim extends App { object MyTopLevelSim extends App {
SimConfig.withWave.doSim(new MyTopLevel) { dut => SimConfig.withWave.doSim(MyTopLevel()) { dut =>
// Fork a process to generate the reset and the clock on the dut // Fork a process to generate the reset and the clock on the dut
dut.clockDomain.forkStimulus(period = 10) dut.clockDomain.forkStimulus(period = 10)