diff --git a/src/main/scala/mylib/MyTopLevelFormal.scala b/src/main/scala/mylib/MyTopLevelFormal.scala
index 7980bf4..7047665 100644
--- a/src/main/scala/mylib/MyTopLevelFormal.scala
+++ b/src/main/scala/mylib/MyTopLevelFormal.scala
@@ -9,7 +9,7 @@ object MyTopLevelFormal extends App {
   FormalConfig
     .withBMC(10)
     .doVerify(new Component {
-      val dut = FormalDut(new MyTopLevel)
+      val dut = FormalDut(MyTopLevel())
 
       // Ensure the formal test start with a reset
       assumeInitial(clockDomain.isResetActive)
diff --git a/src/main/scala/mylib/MyTopLevelGen.scala b/src/main/scala/mylib/MyTopLevelGen.scala
index c823530..cbcaa0b 100644
--- a/src/main/scala/mylib/MyTopLevelGen.scala
+++ b/src/main/scala/mylib/MyTopLevelGen.scala
@@ -4,12 +4,12 @@ import spinal.core._
 
 object MyTopLevelVerilog extends App {
   // Generate the MyTopLevel's Verilog
-  SpinalVerilog(new MyTopLevel)
+  SpinalVerilog(MyTopLevel())
 }
 
 object MyTopLevelVhdl extends App {
   // Generate the MyTopLevel's VHDL
-  SpinalVhdl(new MyTopLevel)
+  SpinalVhdl(MyTopLevel())
 }
 
 // Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one
@@ -21,5 +21,5 @@ object MySpinalConfig
 
 object MyTopLevelVerilogWithCustomConfig extends App {
   // Generate the MyTopLevel's Verilog using the above custom configuration.
-  MySpinalConfig.generateVerilog(new MyTopLevel)
+  MySpinalConfig.generateVerilog(MyTopLevel())
 }
diff --git a/src/main/scala/mylib/MyTopLevelSim.scala b/src/main/scala/mylib/MyTopLevelSim.scala
index 7d19427..1442a16 100644
--- a/src/main/scala/mylib/MyTopLevelSim.scala
+++ b/src/main/scala/mylib/MyTopLevelSim.scala
@@ -4,7 +4,7 @@ import spinal.core._
 import spinal.core.sim._
 
 object MyTopLevelSim extends App {
-  SimConfig.withWave.doSim(new MyTopLevel) { dut =>
+  SimConfig.withWave.doSim(MyTopLevel()) { dut =>
     // Fork a process to generate the reset and the clock on the dut
     dut.clockDomain.forkStimulus(period = 10)