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add tb folder

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Côme ALLART
2022-12-07 20:38:14 +01:00
parent bcae56d0c7
commit 789f0f18d5
6 changed files with 3 additions and 1 deletions
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1
build.sbt
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@@ -10,6 +10,7 @@ val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-
lazy val projectname = (project in file(".")) lazy val projectname = (project in file("."))
.settings( .settings(
Compile / scalaSource := baseDirectory.value / "hw" / "spinal", Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
Test / scalaSource := baseDirectory.value / "tb" / "spinal",
libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin) libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
) )

3
build.sc
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@@ -6,7 +6,8 @@ object projectname extends SbtModule {
def scalaVersion = "2.12.16" def scalaVersion = "2.12.16"
override def millSourcePath = os.pwd override def millSourcePath = os.pwd
def sources = T.sources( def sources = T.sources(
millSourcePath / "hw" / "spinal" millSourcePath / "hw" / "spinal",
millSourcePath / "tb" / "spinal"
) )
def ivyDeps = Agg( def ivyDeps = Agg(
ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion", ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion",

0
hw/spinal/projectname/MyTopLevelFormal.scala → tb/spinal/projectname/MyTopLevelFormal.scala
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0
hw/spinal/projectname/MyTopLevelSim.scala → tb/spinal/projectname/MyTopLevelSim.scala
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0
tb/verilog/.gitignore vendored Normal file
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tb/vhdl/.gitignore vendored Normal file
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