From 789f0f18d517ef4ec78b54510b96e8a6e111fe02 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?C=C3=B4me=20ALLART?= <numero_744@net-c.com>
Date: Wed, 7 Dec 2022 20:38:14 +0100
Subject: [PATCH] add tb folder

---
 build.sbt                                            | 1 +
 build.sc                                             | 3 ++-
 {hw => tb}/spinal/projectname/MyTopLevelFormal.scala | 0
 {hw => tb}/spinal/projectname/MyTopLevelSim.scala    | 0
 tb/verilog/.gitignore                                | 0
 tb/vhdl/.gitignore                                   | 0
 6 files changed, 3 insertions(+), 1 deletion(-)
 rename {hw => tb}/spinal/projectname/MyTopLevelFormal.scala (100%)
 rename {hw => tb}/spinal/projectname/MyTopLevelSim.scala (100%)
 create mode 100644 tb/verilog/.gitignore
 create mode 100644 tb/vhdl/.gitignore

diff --git a/build.sbt b/build.sbt
index f13071e..b9536bd 100644
--- a/build.sbt
+++ b/build.sbt
@@ -10,6 +10,7 @@ val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-
 lazy val projectname = (project in file("."))
   .settings(
     Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
+    Test / scalaSource := baseDirectory.value / "tb" / "spinal",
     libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
   )
 
diff --git a/build.sc b/build.sc
index 96bf792..afb380d 100644
--- a/build.sc
+++ b/build.sc
@@ -6,7 +6,8 @@ object projectname extends SbtModule {
   def scalaVersion = "2.12.16"
   override def millSourcePath = os.pwd
   def sources = T.sources(
-    millSourcePath / "hw" / "spinal"
+    millSourcePath / "hw" / "spinal",
+    millSourcePath / "tb" / "spinal"
   )
   def ivyDeps = Agg(
     ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion",
diff --git a/hw/spinal/projectname/MyTopLevelFormal.scala b/tb/spinal/projectname/MyTopLevelFormal.scala
similarity index 100%
rename from hw/spinal/projectname/MyTopLevelFormal.scala
rename to tb/spinal/projectname/MyTopLevelFormal.scala
diff --git a/hw/spinal/projectname/MyTopLevelSim.scala b/tb/spinal/projectname/MyTopLevelSim.scala
similarity index 100%
rename from hw/spinal/projectname/MyTopLevelSim.scala
rename to tb/spinal/projectname/MyTopLevelSim.scala
diff --git a/tb/verilog/.gitignore b/tb/verilog/.gitignore
new file mode 100644
index 0000000..e69de29
diff --git a/tb/vhdl/.gitignore b/tb/vhdl/.gitignore
new file mode 100644
index 0000000..e69de29