Clearning + Verilog

src/main/scala/MyCode/TopLevel.scala

@@ -23,24 +23,25 @@ import spinal.lib._
 
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in Bool
-    val cond1 = in Bool
-    val flag = out Bool
-    val state = out UInt(8 bit)
+    val cond0 = in  Bool
+    val cond1 = in  Bool
+    val flag  = out Bool
+    val state = out UInt(8 bits)
   }
-  val counter = Reg(UInt(8 bit)) init(0)
+  val counter = Reg(UInt(8 bits)) init(0)
 
   when(io.cond0){
     counter := counter + 1
   }
 
   io.state := counter
-  io.flag := (counter === 0) | io.cond1
+  io.flag  := (counter === 0) | io.cond1
 }
 
 object MyTopLevel {
   def main(args: Array[String]) {
     SpinalVhdl(new MyTopLevel)
+    //SpinalVerilog(new MyTopLevel)
   }
 }