withAssembly

.gitignore

@@ -11,21 +11,15 @@ target
 lib_managed/
 src_managed/
 project/boot/
-project/project
 project/plugins/project/
 
 # Scala-IDE specific
 .scala_dependencies
 .worksheet
-.bloop
 
 .idea
 out
 
-# Metals
-.metals
-project/metals.sbt
-
 # Eclipse
 bin/
 .classpath

.mill-version

@@ -1 +0,0 @@
-0.9.8

.scalafmt.conf

@@ -1,5 +0,0 @@
-version = 3.6.0
-runner.dialect = scala212
-align.preset = some
-maxColumn = 120
-docstrings.wrap = no

README.md

@@ -21,9 +21,8 @@ sudo update-alternatives --config javac
 You need to install SBT
 
 ```sh
-echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
-echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
-curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo apt-key add
+echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list
+sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823
 sudo apt-get update
 sudo apt-get install sbt
 ```
@@ -37,7 +36,7 @@ unsetenv VERILATOR_ROOT  # For csh; ignore error if on bash
 unset VERILATOR_ROOT  # For bash
 cd verilator
 git pull        # Make sure we're up-to-date
-git checkout v4.216
+git checkout verilator_3_916
 autoconf        # Create ./configure script
 ./configure
 make -j$(nproc)
@@ -59,13 +58,13 @@ Open a terminal in the root of it and run "sbt run". At the first execution, the
 cd SpinalTemplateSbt
 
 //If you want to generate the Verilog of your design
-sbt "runMain projectname.MyTopLevelVerilog"
+sbt "runMain mylib.MyTopLevelVerilog"
 
 //If you want to generate the VHDL of your design
-sbt "runMain projectname.MyTopLevelVhdl"
+sbt "runMain mylib.MyTopLevelVhdl"
 
 //If you want to run the scala written testbench
-sbt "runMain projectname.MyTopLevelSim"
+sbt "runMain mylib.MyTopLevelSim"
 ```
 
 The top level spinal code is defined into src\main\scala\mylib
@@ -90,8 +89,6 @@ Normally, this must generate an MyTopLevel.v output files.
 
 ## Basics, with Eclipse and its scala plugin
 
-First, i "strongly" suggest to use intellij idea instead.
-
 You need to install :
 
 - Java JDK
@@ -103,38 +100,9 @@ You need to install :
 And do the following :
 
 - Clone or download this repository.
-- Revert changes from https://github.com/SpinalHDL/SpinalTemplateSbt/commit/173bbb9bb8cbf70087339104f6ebced9321908dd
 - Run ```sbt eclipse``` in the ```SpinalTemplateSbt``` directory.
 - Import the eclipse project from eclipse.
 - In the project (eclipse project GUI), right click on src/main/scala/mylib/MyTopLevel.scala, right click on MyTopLevelVerilog, and select run it
 
 Normally, this must generate output file ```MyTopLevel.v```.
 
-## Mill Support (Experimental)
-
-This Spinal Base Project contains support for the [Mill build tool](https://com-lihaoyi.github.io/mill).
-
-The prerequisites are the same as for using SBT, except for sbt itself. Additionally, the ```mill``` executable needs to be installed on the path. Download it to ```/usr/local/bin/mill``` or ```~/bin/mill``` according to the [installation instructions](https://com-lihaoyi.github.io/mill/mill/Intro_to_Mill.html#_installation).
-
-You can clone and use this repository in the following way.
-
-```sh
-git clone https://github.com/SpinalHDL/SpinalTemplateSbt.git
-```
-
-Open a terminal in the root of it and execute your favorite mill command. At the first execution, the process could take some seconds
-
-```sh
-cd SpinalTemplateSbt
-
-//If you want to generate the Verilog of your design
-mill projectname.runMain projectname.MyTopLevelVerilog
-
-//If you want to generate the VHDL of your design
-mill projectname.runMain projectname.MyTopLevelVhdl
-
-//If you want to run the scala written testbench
-mill projectname.runMain projectname.MyTopLevelSim
-```
-
-The top level spinal code is defined into src\main\scala\mylib

build.sbt

@@ -1,16 +1,13 @@
-ThisBuild / version := "1.0"
-ThisBuild / scalaVersion := "2.12.16"
-ThisBuild / organization := "org.example"
+name := "SpinalTemplateSbt"
+version := "1.0"
+scalaVersion := "2.11.12"
+val spinalVersion = "1.4.0"
 
-val spinalVersion = "1.7.3"
-val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
-val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
-val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
-
-lazy val projectname = (project in file("."))
-  .settings(
-    Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
-    libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
+libraryDependencies ++= Seq(
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % spinalVersion,
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % spinalVersion,
+  compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion)
 )
 
 fork := true
+EclipseKeys.withSource := true

build.sc

@@ -1,16 +0,0 @@
-import mill._, scalalib._
-
-val spinalVersion = "1.7.3"
-
-object projectname extends SbtModule {
-  def scalaVersion = "2.12.16"
-  override def millSourcePath = os.pwd
-  def sources = T.sources(
-    millSourcePath / "hw" / "spinal"
-  )
-  def ivyDeps = Agg(
-    ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion",
-    ivy"com.github.spinalhdl::spinalhdl-lib:$spinalVersion"
-  )
-  def scalacPluginIvyDeps = Agg(ivy"com.github.spinalhdl::spinalhdl-idsl-plugin:$spinalVersion")
-}

hw/gen/.gitignore

@@ -1 +0,0 @@
-*

hw/spinal/projectname/Config.scala

@@ -1,16 +0,0 @@
-package projectname
-
-import spinal.core._
-import spinal.core.sim._
-
-object Config {
-  def spinal = SpinalConfig(
-    targetDirectory = "hw/gen",
-    defaultConfigForClockDomains = ClockDomainConfig(
-      resetActiveLevel = HIGH
-    ),
-    onlyStdLogicVectorAtTopLevelIo = true
-  )
-
-  def sim = SimConfig.withConfig(spinal).withFstWave
-}

hw/spinal/projectname/MyTopLevel.scala

@@ -1,30 +0,0 @@
-package projectname
-
-import spinal.core._
-
-// Hardware definition
-case class MyTopLevel() extends Component {
-  val io = new Bundle {
-    val cond0 = in  Bool()
-    val cond1 = in  Bool()
-    val flag  = out Bool()
-    val state = out UInt(8 bits)
-  }
-
-  val counter = Reg(UInt(8 bits)) init 0
-
-  when(io.cond0) {
-    counter := counter + 1
-  }
-
-  io.state := counter
-  io.flag := (counter === 0) | io.cond1
-}
-
-object MyTopLevelVerilog extends App {
-  Config.spinal.generateVerilog(MyTopLevel())
-}
-
-object MyTopLevelVhdl extends App {
-  Config.spinal.generateVhdl(MyTopLevel())
-}

hw/spinal/projectname/MyTopLevelFormal.scala

@@ -1,24 +0,0 @@
-package projectname
-
-import spinal.core._
-import spinal.core.formal._
-
-// You need SymbiYosys to be installed.
-// See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
-object MyTopLevelFormal extends App {
-  FormalConfig
-    .withBMC(10)
-    .doVerify(new Component {
-      val dut = FormalDut(MyTopLevel())
-
-      // Ensure the formal test start with a reset
-      assumeInitial(clockDomain.isResetActive)
-
-      // Provide some stimulus
-      anyseq(dut.io.cond0)
-      anyseq(dut.io.cond1)
-
-      // Check the state initial value and increment
-      assert(dut.io.state === past(dut.io.state + U(dut.io.cond0)).init(0))
-    })
-}

hw/spinal/projectname/MyTopLevelSim.scala

@@ -1,31 +0,0 @@
-package projectname
-
-import spinal.core._
-import spinal.core.sim._
-
-object MyTopLevelSim extends App {
-  Config.sim.compile(MyTopLevel()).doSim { dut =>
-    // Fork a process to generate the reset and the clock on the dut
-    dut.clockDomain.forkStimulus(period = 10)
-
-    var modelState = 0
-    for (idx <- 0 to 99) {
-      // Drive the dut inputs with random values
-      dut.io.cond0.randomize()
-      dut.io.cond1.randomize()
-
-      // Wait a rising edge on the clock
-      dut.clockDomain.waitRisingEdge()
-
-      // Check that the dut values match with the reference model ones
-      val modelFlag = modelState == 0 || dut.io.cond1.toBoolean
-      assert(dut.io.state.toInt == modelState)
-      assert(dut.io.flag.toBoolean == modelFlag)
-
-      // Update the reference model value
-      if (dut.io.cond0.toBoolean) {
-        modelState = (modelState + 1) & 0xff
-      }
-    }
-  }
-}

project/build.properties

@@ -1 +1 @@
-sbt.version=1.6.0
+sbt.version=1.3.3

project/plugins.sbt

@@ -1 +1,4 @@
-addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.4.6")
+addSbtPlugin("com.typesafe.sbteclipse" % "sbteclipse-plugin" % "5.2.4")
+
+addSbtPlugin("com.eed3si9n" % "sbt-assembly" % "0.14.10")
+

src/main/scala/mylib/MyTopLevel.scala

@@ -0,0 +1,67 @@
+/*
+ * SpinalHDL
+ * Copyright (c) Dolu, All rights reserved.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 3.0 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library.
+ */
+
+package mylib
+
+import spinal.core._
+import spinal.lib._
+
+import scala.util.Random
+
+//Hardware definition
+class MyTopLevel extends Component {
+  val io = new Bundle {
+    val cond0 = in  Bool
+    val cond1 = in  Bool
+    val flag  = out Bool
+    val state = out UInt(8 bits)
+  }
+  val counter = Reg(UInt(8 bits)) init(0)
+
+  when(io.cond0){
+    counter := counter + 1
+  }
+
+  io.state := counter
+  io.flag  := (counter === 0) | io.cond1
+}
+
+//Generate the MyTopLevel's Verilog
+object MyTopLevelVerilog {
+  def main(args: Array[String]) {
+    SpinalVerilog(new MyTopLevel)
+  }
+}
+
+//Generate the MyTopLevel's VHDL
+object MyTopLevelVhdl {
+  def main(args: Array[String]) {
+    SpinalVhdl(new MyTopLevel)
+  }
+}
+
+
+//Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere
+object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC))
+
+//Generate the MyTopLevel's Verilog using the above custom configuration.
+object MyTopLevelVerilogWithCustomConfig {
+  def main(args: Array[String]) {
+    MySpinalConfig.generateVerilog(new MyTopLevel)
+  }
+}

src/main/scala/mylib/MyTopLevelSim.scala

@@ -0,0 +1,38 @@
+package mylib
+
+import spinal.core._
+import spinal.sim._
+import spinal.core.sim._
+
+import scala.util.Random
+
+
+//MyTopLevel's testbench
+object MyTopLevelSim {
+  def main(args: Array[String]) {
+    SimConfig.withWave.doSim(new MyTopLevel){dut =>
+      //Fork a process to generate the reset and the clock on the dut
+      dut.clockDomain.forkStimulus(period = 10)
+
+      var modelState = 0
+      for(idx <- 0 to 99){
+        //Drive the dut inputs with random values
+        dut.io.cond0 #= Random.nextBoolean()
+        dut.io.cond1 #= Random.nextBoolean()
+
+        //Wait a rising edge on the clock
+        dut.clockDomain.waitRisingEdge()
+
+        //Check that the dut values match with the reference model ones
+        val modelFlag = modelState == 0 || dut.io.cond1.toBoolean
+        assert(dut.io.state.toInt == modelState)
+        assert(dut.io.flag.toBoolean == modelFlag)
+
+        //Update the reference model value
+        if(dut.io.cond0.toBoolean) {
+          modelState = (modelState + 1) & 0xFF
+        }
+      }
+    }
+  }
+}