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2 Commits

Author SHA1 Message Date
Dolu1990
976ceca3a3 Update Config.scala 
onlyStdLogicVectorAtTopLevelIo = false as it prevent VHDL / GHDL sim
 2025-04-06 14:58:20 +02:00
Côme ALLART
4849860e14 refactor: simplify project structure 2022-11-25 10:39:48 +01:00