big update

- remove not supported anymore procedural syntax for main functions
- use App instead of main
- auto format
- move comments to have more user-friendly access to "run" and "debug"
  button for Apps
- move generators to dedicated new file

.gitignore

@@ -11,17 +11,20 @@ target
 lib_managed/
 src_managed/
 project/boot/
+project/project
 project/plugins/project/
 
 # Scala-IDE specific
 .scala_dependencies
 .worksheet
+.bloop
 
 .idea
 out
 
 # Metals
 .metals
+project/metals.sbt
 
 # Eclipse
 bin/

src/main/scala/mylib/MyTopLevel.scala

@@ -1,27 +1,6 @@
-/*
- * SpinalHDL
- * Copyright (c) Dolu, All rights reserved.
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 3.0 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library.
- */
-
 package mylib
 
 import spinal.core._
-import spinal.lib._
-
-import scala.util.Random
 
 // Hardware definition
 class MyTopLevel extends Component {
@@ -31,7 +10,8 @@ class MyTopLevel extends Component {
     val flag = out Bool ()
     val state = out UInt (8 bits)
   }
-  val counter = Reg(UInt(8 bits)) init(0)
+
+  val counter = Reg(UInt(8 bits)) init 0
 
   when(io.cond0) {
     counter := counter + 1
@@ -40,28 +20,3 @@ class MyTopLevel extends Component {
   io.state := counter
   io.flag := (counter === 0) | io.cond1
 }
-
-//Generate the MyTopLevel's Verilog
-object MyTopLevelVerilog {
-  def main(args: Array[String]) {
-    SpinalVerilog(new MyTopLevel)
-  }
-}
-
-//Generate the MyTopLevel's VHDL
-object MyTopLevelVhdl {
-  def main(args: Array[String]) {
-    SpinalVhdl(new MyTopLevel)
-  }
-}
-
-
-//Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere
-object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC))
-
-//Generate the MyTopLevel's Verilog using the above custom configuration.
-object MyTopLevelVerilogWithCustomConfig {
-  def main(args: Array[String]) {
-    MySpinalConfig.generateVerilog(new MyTopLevel)
-  }
-}

src/main/scala/mylib/MyTopLevelFormal.scala

@@ -5,9 +5,10 @@ import spinal.core.formal._
 
 // You need SymbiYosys to be installed.
 // See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
-object MyTopLevelFormal {
-  def main(args: Array[String]) {
-    FormalConfig.withBMC(10).doVerify(new Component {
+object MyTopLevelFormal extends App {
+  FormalConfig
+    .withBMC(10)
+    .doVerify(new Component {
       val dut = FormalDut(new MyTopLevel)
 
       // Ensure the formal test start with a reset
@@ -21,4 +22,3 @@ object MyTopLevelFormal {
       assert(dut.io.state === past(dut.io.state + U(dut.io.cond0)).init(0))
     })
 }
-}

src/main/scala/mylib/MyTopLevelGen.scala

@@ -0,0 +1,25 @@
+package mylib
+
+import spinal.core._
+
+object MyTopLevelVerilog extends App {
+  // Generate the MyTopLevel's Verilog
+  SpinalVerilog(new MyTopLevel)
+}
+
+object MyTopLevelVhdl extends App {
+  // Generate the MyTopLevel's VHDL
+  SpinalVhdl(new MyTopLevel)
+}
+
+// Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one
+// This configuration can be resued everywhere
+object MySpinalConfig
+    extends SpinalConfig(
+      defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC)
+    )
+
+object MyTopLevelVerilogWithCustomConfig extends App {
+  // Generate the MyTopLevel's Verilog using the above custom configuration.
+  MySpinalConfig.generateVerilog(new MyTopLevel)
+}

src/main/scala/mylib/MyTopLevelSim.scala

@@ -1,15 +1,9 @@
 package mylib
 
 import spinal.core._
-import spinal.sim._
 import spinal.core.sim._
 
-import scala.util.Random
-
-
-//MyTopLevel's testbench
-object MyTopLevelSim {
-  def main(args: Array[String]) {
+object MyTopLevelSim extends App {
   SimConfig.withWave.doSim(new MyTopLevel) { dut =>
     // Fork a process to generate the reset and the clock on the dut
     dut.clockDomain.forkStimulus(period = 10)
@@ -17,8 +11,8 @@ object MyTopLevelSim {
     var modelState = 0
     for (idx <- 0 to 99) {
       // Drive the dut inputs with random values
-        dut.io.cond0 #= Random.nextBoolean()
-        dut.io.cond1 #= Random.nextBoolean()
+      dut.io.cond0.randomize()
+      dut.io.cond1.randomize()
 
       // Wait a rising edge on the clock
       dut.clockDomain.waitRisingEdge()
@@ -30,8 +24,7 @@ object MyTopLevelSim {
 
       // Update the reference model value
       if (dut.io.cond0.toBoolean) {
-          modelState = (modelState + 1) & 0xFF
-        }
+        modelState = (modelState + 1) & 0xff
       }
     }
   }