mirror of
https://github.com/SpinalHDL/SpinalTemplateSbt.git
synced 2025-10-25 08:48:45 +08:00
big update
- remove not supported anymore procedural syntax for main functions - use App instead of main - auto format - move comments to have more user-friendly access to "run" and "debug" button for Apps - move generators to dedicated new file
This commit is contained in:
25
src/main/scala/mylib/MyTopLevelGen.scala
Normal file
25
src/main/scala/mylib/MyTopLevelGen.scala
Normal file
@@ -0,0 +1,25 @@
|
||||
package mylib
|
||||
|
||||
import spinal.core._
|
||||
|
||||
object MyTopLevelVerilog extends App {
|
||||
// Generate the MyTopLevel's Verilog
|
||||
SpinalVerilog(new MyTopLevel)
|
||||
}
|
||||
|
||||
object MyTopLevelVhdl extends App {
|
||||
// Generate the MyTopLevel's VHDL
|
||||
SpinalVhdl(new MyTopLevel)
|
||||
}
|
||||
|
||||
// Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one
|
||||
// This configuration can be resued everywhere
|
||||
object MySpinalConfig
|
||||
extends SpinalConfig(
|
||||
defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC)
|
||||
)
|
||||
|
||||
object MyTopLevelVerilogWithCustomConfig extends App {
|
||||
// Generate the MyTopLevel's Verilog using the above custom configuration.
|
||||
MySpinalConfig.generateVerilog(new MyTopLevel)
|
||||
}
|
||||
Reference in New Issue
Block a user