From bcae56d0c728238260b1e306cd8530217fdb27e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20ALLART?= Date: Wed, 7 Dec 2022 20:02:11 +0100 Subject: [PATCH 1/2] add helpers to quickly write beautiful code --- .scalafmt.conf | 37 ++++++- .vscode/SpinalHDL.code-snippets | 190 ++++++++++++++++++++++++++++++++ 2 files changed, 226 insertions(+), 1 deletion(-) create mode 100644 .vscode/SpinalHDL.code-snippets diff --git a/.scalafmt.conf b/.scalafmt.conf index 92dc1fc..e5728d5 100644 --- a/.scalafmt.conf +++ b/.scalafmt.conf @@ -1,5 +1,40 @@ version = 3.6.0 runner.dialect = scala212 align.preset = some -maxColumn = 120 +align.tokens."+" = [ + { + code = "=" + owners = [{ + regex = "Defn\\.Val" + }] + } + { + code = ":=" + owners = [{ + regex = "Term\\.ApplyInfix" + parents = ["Term\\.Block|Template"] + }] + } + { + code = "#=" + owners = [{ + regex = "Term\\.ApplyInfix" + parents = ["Term\\.Block|Template"] + }] + } + { + code = "port" + owners = [{ + regex = "Term\\.ApplyInfix" + parents = ["Defn\\.Val"] + }] + } + { + code = "->" + owners = [{ + regex = "Term\\.ApplyInfix" + }] + } +] docstrings.wrap = no +docstrings.oneline = fold diff --git a/.vscode/SpinalHDL.code-snippets b/.vscode/SpinalHDL.code-snippets new file mode 100644 index 0000000..514859e --- /dev/null +++ b/.vscode/SpinalHDL.code-snippets @@ -0,0 +1,190 @@ +{ + "Import spinal.core": { + "scope": "scala", + "prefix": "importcore", + "body": ["import spinal.core._", ""] + }, + + "Import spinal.lib": { + "scope": "scala", + "prefix": "importlib", + "body": ["import spinal.lib.${1:_}", ""] + }, + + "Import spinal.core.sim": { + "scope": "scala", + "prefix": "importsim", + "body": ["import spinal.core.sim._", ""] + }, + + "New component": { + "scope": "scala", + "prefix": "component", + "body": [ + "case class $1($2) extends Component {", + " val io = new Bundle {", + " $0", + " }", + "", + " ", + "}" + ], + }, + + "Component to function": { + "scope": "scala", + "prefix": "fncomp", + "body": [ + "object ${1/\\(.*//} {", + " def apply($2: $3): $4 = {", + " val ${1/([^(]*).*/${1:/camelcase}/} = $1($6)", + " ${1/([^(]*).*/${1:/camelcase}/}.io.$2 := $2", + " ${1/([^(]*).*/${1:/camelcase}/}.io.$5", + " }", + "}" + ], + }, + + "Component to function2": { + "scope": "scala", + "prefix": "fncomp2", + "body": [ + "object ${1/\\(.*//} {", + " def apply($2: $3, $4: $5): $6 = {", + " val ${1/([^(]*).*/${1:/camelcase}/} = $1($8)", + " ${1/([^(]*).*/${1:/camelcase}/}.io.$2 := $2", + " ${1/([^(]*).*/${1:/camelcase}/}.io.$4 := $4", + " ${1/([^(]*).*/${1:/camelcase}/}.io.$7", + " }", + "}" + ], + }, + + "New configurable component": { + "scope": "scala", + "prefix": "compcfg", + "body": [ + "case class ${2:${1}Cfg} (", + " $3", + ")", + "", + "class $1(cfg: $2) extends Component {", + " val io = new Bundle {", + " $0", + " }", + "", + " ", + "}" + ], + }, + + "New entity/architecture-like": { + "scope": "scala", + "prefix": "entarch", + "body": [ + "abstract class $1$2 extends Component {", + " val io = new Bundle {", + " $0", + " }", + "}", + "", + "class $1$3 extends $1$4 {", + " ", + "}", + ], + }, + + "New input": { + "scope": "scala", + "prefix": "pin", + "body": "val $1 = in port ", + }, + + "New output": { + "scope": "scala", + "prefix": "pout", + "body": "val $1 = out port ", + }, + + "New master port": { + "scope": "scala", + "prefix": "pmaster", + "body": "val $1 = master port ", + }, + + "New slave port": { + "scope": "scala", + "prefix": "pslave", + "body": "val $1 = slave port ", + }, + + "Bits": { + "scope": "scala", + "prefix": "nbits", + "body": "Bits($1 bits)", + }, + + "UInt": { + "scope": "scala", + "prefix": "nuint", + "body": "UInt($1 bits)", + }, + + "SInt": { + "scope": "scala", + "prefix": "nsint", + "body": "SInt($1 bits)", + }, + + "...ing flag": { + "scope": "scala", + "prefix": "doing", + "body": ["val ${2:${1}ing} = False", "def $1(): Unit = $2 := True", ""] + }, + + "...Flag flag": { + "scope": "scala", + "prefix": "flag", + "body": ["val ${2:${1}Flag} = False", "def $1(): Unit = $2 := True", ""] + }, + + "'def' function mux": { + "scope": "scala", + "prefix": "fnmux", + "body": ["$1 := $2", "def $3(): Unit = $1 := $0"] + }, + + "BlackBox wrapper": { + "scope": "scala", + "prefix": "blackboxwrapper", + "body": [ + "class $1 extends Area {", + " val io = new Bundle {", + " ${0:// Direction-less Spinal ports}", + " }", + "", + " class $1 extends BlackBox {", + " // Ports of the blackboxed item", + " }", + "", + " val bb = new $1", + " bb.setPartialName(\"\")", + "", + " // Connection logic", + "}" + ] + }, + + "State machine": { + "scope": "scala", + "prefix": "fsm", + "body": [ + "val $1 = new StateMachine {", + " val $2, $3 = new State", + " setEntry($2)", + "", + " $0", + "}" + ] + } +} \ No newline at end of file From 789f0f18d517ef4ec78b54510b96e8a6e111fe02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?C=C3=B4me=20ALLART?= Date: Wed, 7 Dec 2022 20:38:14 +0100 Subject: [PATCH 2/2] add tb folder --- build.sbt | 1 + build.sc | 3 ++- {hw => tb}/spinal/projectname/MyTopLevelFormal.scala | 0 {hw => tb}/spinal/projectname/MyTopLevelSim.scala | 0 tb/verilog/.gitignore | 0 tb/vhdl/.gitignore | 0 6 files changed, 3 insertions(+), 1 deletion(-) rename {hw => tb}/spinal/projectname/MyTopLevelFormal.scala (100%) rename {hw => tb}/spinal/projectname/MyTopLevelSim.scala (100%) create mode 100644 tb/verilog/.gitignore create mode 100644 tb/vhdl/.gitignore diff --git a/build.sbt b/build.sbt index f13071e..b9536bd 100644 --- a/build.sbt +++ b/build.sbt @@ -10,6 +10,7 @@ val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl- lazy val projectname = (project in file(".")) .settings( Compile / scalaSource := baseDirectory.value / "hw" / "spinal", + Test / scalaSource := baseDirectory.value / "tb" / "spinal", libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin) ) diff --git a/build.sc b/build.sc index 96bf792..afb380d 100644 --- a/build.sc +++ b/build.sc @@ -6,7 +6,8 @@ object projectname extends SbtModule { def scalaVersion = "2.12.16" override def millSourcePath = os.pwd def sources = T.sources( - millSourcePath / "hw" / "spinal" + millSourcePath / "hw" / "spinal", + millSourcePath / "tb" / "spinal" ) def ivyDeps = Agg( ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion", diff --git a/hw/spinal/projectname/MyTopLevelFormal.scala b/tb/spinal/projectname/MyTopLevelFormal.scala similarity index 100% rename from hw/spinal/projectname/MyTopLevelFormal.scala rename to tb/spinal/projectname/MyTopLevelFormal.scala diff --git a/hw/spinal/projectname/MyTopLevelSim.scala b/tb/spinal/projectname/MyTopLevelSim.scala similarity index 100% rename from hw/spinal/projectname/MyTopLevelSim.scala rename to tb/spinal/projectname/MyTopLevelSim.scala diff --git a/tb/verilog/.gitignore b/tb/verilog/.gitignore new file mode 100644 index 0000000..e69de29 diff --git a/tb/vhdl/.gitignore b/tb/vhdl/.gitignore new file mode 100644 index 0000000..e69de29