diff --git a/README.md b/README.md index 75f4d58..def3c61 100644 --- a/README.md +++ b/README.md @@ -7,7 +7,7 @@ This repository is a base SBT project added to help non Scala/SBT native people You need to install Java JDK and SBT ```sh -sudo apt-get install openjdk-7-jdk +sudo apt-get install openjdk-8-jdk echo "deb https://dl.bintray.com/sbt/debian /" | sudo tee -a /etc/apt/sources.list.d/sbt.list sudo apt-key adv --keyserver hkp://keyserver.ubuntu.com:80 --recv 2EE0EA64E40A89B84B2DF73499E82A75642AC823 @@ -15,6 +15,25 @@ sudo apt-get update sudo apt-get install sbt ``` +If you want to run the scala written testbench, you have to be on linux and have Verilator installed (a recent version) : + +```sh +sudo apt-get install git make autoconf g++ flex bison -y # First time prerequisites +git clone http://git.veripool.org/git/verilator # Only first time +unsetenv VERILATOR_ROOT # For csh; ignore error if on bash +unset VERILATOR_ROOT # For bash +cd verilator +git pull # Make sure we're up-to-date +git tag # See what versions exist +autoconf # Create ./configure script +./configure +make -j$(nproc) +sudo make install +cd .. +echo "DONE" + +``` + Clone or download this repository. ```sh @@ -25,11 +44,18 @@ Open a terminal in the root of it and run "sbt run". At the first execution, the ```sh cd SpinalBaseProject -sbt run + +//If you want to generate the Verilog of your design +sbt "run-main mylib.MyTopLevelVerilog" + +//If you want to generate the VHDL of your design +sbt "run-main mylib.MyTopLevelVhdl" + +//If you want to run the scala written testbench +sbt "run-main mylib.MyTopLevelSim" ``` -Normally, this "sbt run" command must generate an output files named MyTopLevel.vhd. -The top level spinal code is defined into src\main\scala\MyCode +The top level spinal code is defined into src\main\scala\mylib ## Basics, with Intellij IDEA and its scala plugin @@ -45,9 +71,9 @@ And do the following : - Clone or download this repository. - In Intellij IDEA, "import project" with the root of this repository, Import project from external model SBT - In addition maybe you need to specify some path like JDK to Intellij -- In the project (Intellij project GUI), right click on src/main/scala/MyCode/TopLevel.scala and select "Run MyTopLevel" +- In the project (Intellij project GUI), go in src/main/scala/mylib/MyTopLevel.scala, right click on MyTopLevelVerilog, "Run MyTopLevelVerilog" -Normally, this must generate an MyTopLevel.vhd output files. +Normally, this must generate an MyTopLevel.v output files. ## Basics, with Eclipse and its scala plugin @@ -64,7 +90,7 @@ And do the following : - Clone or download this repository. - Run ```sbt eclipse``` in the ```SpinalBaseProject``` directory. - Import the eclipse project from eclipse. -- In the project (eclips project GUI), right click on src/main/scala/MyCode/TopLeve.scala and select "Run as" > "Scala application" +- In the project (eclipse project GUI), right click on src/main/scala/mylib/MyTopLevel.scala, right click on MyTopLevelVerilog, and select run it -Normally, this must generate output file ```MyTopLevel.vhd```. +Normally, this must generate output file ```MyTopLevel.v```. diff --git a/src/main/scala/MyCode/TopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala similarity index 53% rename from src/main/scala/MyCode/TopLevel.scala rename to src/main/scala/mylib/MyTopLevel.scala index af0c7b7..db590f0 100644 --- a/src/main/scala/MyCode/TopLevel.scala +++ b/src/main/scala/mylib/MyTopLevel.scala @@ -16,7 +16,7 @@ * License along with this library. */ -package MyCode +package mylib import spinal.core._ import spinal.lib._ @@ -56,49 +56,3 @@ object MyTopLevelVhdl { SpinalVhdl(new MyTopLevel) } } - -//MyTopLevel's testbench -object MyTopLevelSim { - def main(args: Array[String]) { - SimConfig(new MyTopLevel).withWave.doManagedSim{dut => - - //Fork a process to generate the reset and the clock on the dut - fork{ - dut.clockDomain.assertReset() - dut.clockDomain.fallingEdge() - sleep(10) - dut.clockDomain.disassertReset() - sleep(10) - while(true){ - dut.clockDomain.clockToggle() - sleep(5) - } - } - - - var idx = 0 - while(idx < 100){ - //Generate random values to drive the reference model and the dut - val cond0, cond1 = Random.nextBoolean() - val oldState = dut.io.state.toInt - - //Drive the dut inputs - dut.io.cond0 #= cond0 - dut.io.cond1 #= cond1 - - //Wait a rising edge on the clock - dut.clockDomain.waitRisingEdge() - - //Calculate the reference model values - val modelState = if(cond0) (oldState + 1) & 0xFF else oldState - val modelFlag = modelState == 0 || cond1 - - //Check that the dut values match with the reference model ones - assert(dut.io.state.toInt == modelState) - assert(dut.io.flag.toBoolean == modelFlag) - - idx += 1 - } - } - } -} diff --git a/src/main/scala/mylib/MyTopLevelSim.scala b/src/main/scala/mylib/MyTopLevelSim.scala new file mode 100644 index 0000000..99b11fd --- /dev/null +++ b/src/main/scala/mylib/MyTopLevelSim.scala @@ -0,0 +1,54 @@ +package mylib + +import spinal.core._ +import spinal.sim._ +import spinal.core.SimManagedApi._ + +import scala.util.Random + + +//MyTopLevel's testbench +object MyTopLevelSim { + def main(args: Array[String]) { + SimConfig(new MyTopLevel).withWave.doManagedSim{dut => + + //Fork a process to generate the reset and the clock on the dut + fork{ + dut.clockDomain.assertReset() + dut.clockDomain.fallingEdge() + sleep(10) + dut.clockDomain.disassertReset() + sleep(10) + while(true){ + dut.clockDomain.clockToggle() + sleep(5) + } + } + + + var idx = 0 + while(idx < 100){ + //Generate random values to drive the reference model and the dut + val cond0, cond1 = Random.nextBoolean() + val oldState = dut.io.state.toInt + + //Drive the dut inputs + dut.io.cond0 #= cond0 + dut.io.cond1 #= cond1 + + //Wait a rising edge on the clock + dut.clockDomain.waitRisingEdge() + + //Calculate the reference model values + val modelState = if(cond0) (oldState + 1) & 0xFF else oldState + val modelFlag = modelState == 0 || cond1 + + //Check that the dut values match with the reference model ones + assert(dut.io.state.toInt == modelState) + assert(dut.io.flag.toBoolean == modelFlag) + + idx += 1 + } + } + } +}