From 86071d797aeeb39612d66d5ccc5429df5a3e2c52 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sun, 16 Sep 2018 13:52:46 +0200
Subject: [PATCH] Add example with custom config

---
 src/main/scala/mylib/MyTopLevel.scala | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/main/scala/mylib/MyTopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala
index 204adce..196d09a 100644
--- a/src/main/scala/mylib/MyTopLevel.scala
+++ b/src/main/scala/mylib/MyTopLevel.scala
@@ -54,3 +54,14 @@ object MyTopLevelVhdl {
     SpinalVhdl(new MyTopLevel)
   }
 }
+
+
+//Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere
+object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC))
+
+//Generate the MyTopLevel's Verilog using the above custom configuration.
+object MyTopLevelVerilogWithCustomConfig {
+  def main(args: Array[String]) {
+    MySpinalConfig.generateVerilog(new MyTopLevel)
+  }
+}
\ No newline at end of file