diff --git a/src/main/scala/mylib/MyTopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala
index 204adce..196d09a 100644
--- a/src/main/scala/mylib/MyTopLevel.scala
+++ b/src/main/scala/mylib/MyTopLevel.scala
@@ -54,3 +54,14 @@ object MyTopLevelVhdl {
     SpinalVhdl(new MyTopLevel)
   }
 }
+
+
+//Define a custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one. This configuration can be resued everywhere
+object MySpinalConfig extends SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC))
+
+//Generate the MyTopLevel's Verilog using the above custom configuration.
+object MyTopLevelVerilogWithCustomConfig {
+  def main(args: Array[String]) {
+    MySpinalConfig.generateVerilog(new MyTopLevel)
+  }
+}
\ No newline at end of file