diff --git a/.gitignore b/.gitignore
index 3e0e5a5..dc09fb4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -36,4 +36,5 @@ bin/
 !tester/src/test/resources/*.vhd
 
 
-*verilatorSim/
\ No newline at end of file
+simWorkspace/
+tmp/
diff --git a/build.sbt b/build.sbt
index b4b6321..a421407 100644
--- a/build.sbt
+++ b/build.sbt
@@ -7,9 +7,10 @@ scalaVersion := "2.11.6"
 EclipseKeys.withSource := true
 
 libraryDependencies ++= Seq(
-  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.4",
-  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.4"
+  "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.0.5",
+  "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.0.5"
 )
 
 addCompilerPlugin("org.scala-lang.plugins" % "scala-continuations-plugin_2.11.6" % "1.0.2")
 scalacOptions += "-P:continuations:enable"
+fork := true
diff --git a/src/main/scala/mylib/MyTopLevelSim.scala b/src/main/scala/mylib/MyTopLevelSim.scala
index dac5b49..9963cc4 100644
--- a/src/main/scala/mylib/MyTopLevelSim.scala
+++ b/src/main/scala/mylib/MyTopLevelSim.scala
@@ -11,11 +11,9 @@ import scala.util.Random
 object MyTopLevelSim {
   def main(args: Array[String]) {
     SimConfig(new MyTopLevel).withWave.doManagedSim{dut =>
-
       //Fork a process to generate the reset and the clock on the dut
       dut.clockDomain.forkStimulus(period = 10)
 
-
       var modelState = 0
       var idx = 0
       while(idx < 100){