refactor: simplify project structure

build.sbt

@@ -7,9 +7,9 @@ val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
 val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
 val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
 
-lazy val mylib = (project in file("."))
+lazy val projectname = (project in file("."))
   .settings(
-    name := "SpinalTemplateSbt",
+    Compile / scalaSource := baseDirectory.value / "hw" / "spinal",
     libraryDependencies ++= Seq(spinalCore, spinalLib, spinalIdslPlugin)
   )
 

build.sc

@@ -2,9 +2,12 @@ import mill._, scalalib._
 
 val spinalVersion = "1.7.3"
 
-object mylib extends SbtModule {
-  def scalaVersion = "2.12.14"
+object projectname extends SbtModule {
+  def scalaVersion = "2.12.16"
   override def millSourcePath = os.pwd
+  def sources = T.sources(
+    millSourcePath / "hw" / "spinal"
+  )
   def ivyDeps = Agg(
     ivy"com.github.spinalhdl::spinalhdl-core:$spinalVersion",
     ivy"com.github.spinalhdl::spinalhdl-lib:$spinalVersion"

hw/gen/.gitignore

@@ -0,0 +1 @@
+*

hw/spinal/projectname/Config.scala

@@ -0,0 +1,16 @@
+package projectname
+
+import spinal.core._
+import spinal.core.sim._
+
+object Config {
+  def spinal = SpinalConfig(
+    targetDirectory = "hw/gen",
+    defaultConfigForClockDomains = ClockDomainConfig(
+      resetActiveLevel = HIGH
+    ),
+    onlyStdLogicVectorAtTopLevelIo = true
+  )
+
+  def sim = SimConfig.withConfig(spinal).withFstWave
+}

hw/spinal/projectname/MyTopLevel.scala

@@ -1,4 +1,4 @@
-package mylib
+package projectname
 
 import spinal.core._
 
@@ -20,3 +20,11 @@ case class MyTopLevel() extends Component {
   io.state := counter
   io.flag := (counter === 0) | io.cond1
 }
+
+object MyTopLevelVerilog extends App {
+  Config.spinal.generateVerilog(MyTopLevel())
+}
+
+object MyTopLevelVhdl extends App {
+  Config.spinal.generateVhdl(MyTopLevel())
+}

hw/spinal/projectname/MyTopLevelFormal.scala

@@ -1,4 +1,4 @@
-package mylib
+package projectname
 
 import spinal.core._
 import spinal.core.formal._

hw/spinal/projectname/MyTopLevelSim.scala

@@ -1,10 +1,10 @@
-package mylib
+package projectname
 
 import spinal.core._
 import spinal.core.sim._
 
 object MyTopLevelSim extends App {
-  SimConfig.withWave.doSim(MyTopLevel()) { dut =>
+  Config.sim.compile(MyTopLevel()).doSim { dut =>
     // Fork a process to generate the reset and the clock on the dut
     dut.clockDomain.forkStimulus(period = 10)
 

src/main/scala/mylib/MyTopLevelGen.scala

@@ -1,25 +0,0 @@
-package mylib
-
-import spinal.core._
-
-object MyTopLevelVerilog extends App {
-  // Generate the MyTopLevel's Verilog
-  SpinalVerilog(MyTopLevel())
-}
-
-object MyTopLevelVhdl extends App {
-  // Generate the MyTopLevel's VHDL
-  SpinalVhdl(MyTopLevel())
-}
-
-// Custom SpinalHDL configuration with synchronous reset instead of the default asynchronous one
-// This configuration can be resued everywhere
-object MySpinalConfig
-    extends SpinalConfig(
-      defaultConfigForClockDomains = ClockDomainConfig(resetKind = SYNC)
-    )
-
-object MyTopLevelVerilogWithCustomConfig extends App {
-  // Generate the MyTopLevel's Verilog using the above custom configuration.
-  MySpinalConfig.generateVerilog(MyTopLevel())
-}