refactor: simplify project structure

hw/spinal/projectname/Config.scala

@@ -0,0 +1,16 @@
+package projectname
+
+import spinal.core._
+import spinal.core.sim._
+
+object Config {
+  def spinal = SpinalConfig(
+    targetDirectory = "hw/gen",
+    defaultConfigForClockDomains = ClockDomainConfig(
+      resetActiveLevel = HIGH
+    ),
+    onlyStdLogicVectorAtTopLevelIo = true
+  )
+
+  def sim = SimConfig.withConfig(spinal).withFstWave
+}

hw/spinal/projectname/MyTopLevel.scala

@@ -0,0 +1,30 @@
+package projectname
+
+import spinal.core._
+
+// Hardware definition
+case class MyTopLevel() extends Component {
+  val io = new Bundle {
+    val cond0 = in  Bool()
+    val cond1 = in  Bool()
+    val flag  = out Bool()
+    val state = out UInt(8 bits)
+  }
+
+  val counter = Reg(UInt(8 bits)) init 0
+
+  when(io.cond0) {
+    counter := counter + 1
+  }
+
+  io.state := counter
+  io.flag := (counter === 0) | io.cond1
+}
+
+object MyTopLevelVerilog extends App {
+  Config.spinal.generateVerilog(MyTopLevel())
+}
+
+object MyTopLevelVhdl extends App {
+  Config.spinal.generateVhdl(MyTopLevel())
+}

hw/spinal/projectname/MyTopLevelFormal.scala

@@ -0,0 +1,24 @@
+package projectname
+
+import spinal.core._
+import spinal.core.formal._
+
+// You need SymbiYosys to be installed.
+// See https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Formal%20verification/index.html#installing-requirements
+object MyTopLevelFormal extends App {
+  FormalConfig
+    .withBMC(10)
+    .doVerify(new Component {
+      val dut = FormalDut(MyTopLevel())
+
+      // Ensure the formal test start with a reset
+      assumeInitial(clockDomain.isResetActive)
+
+      // Provide some stimulus
+      anyseq(dut.io.cond0)
+      anyseq(dut.io.cond1)
+
+      // Check the state initial value and increment
+      assert(dut.io.state === past(dut.io.state + U(dut.io.cond0)).init(0))
+    })
+}

hw/spinal/projectname/MyTopLevelSim.scala

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+package projectname
+
+import spinal.core._
+import spinal.core.sim._
+
+object MyTopLevelSim extends App {
+  Config.sim.compile(MyTopLevel()).doSim { dut =>
+    // Fork a process to generate the reset and the clock on the dut
+    dut.clockDomain.forkStimulus(period = 10)
+
+    var modelState = 0
+    for (idx <- 0 to 99) {
+      // Drive the dut inputs with random values
+      dut.io.cond0.randomize()
+      dut.io.cond1.randomize()
+
+      // Wait a rising edge on the clock
+      dut.clockDomain.waitRisingEdge()
+
+      // Check that the dut values match with the reference model ones
+      val modelFlag = modelState == 0 || dut.io.cond1.toBoolean
+      assert(dut.io.state.toInt == modelState)
+      assert(dut.io.flag.toBoolean == modelFlag)
+
+      // Update the reference model value
+      if (dut.io.cond0.toBoolean) {
+        modelState = (modelState + 1) & 0xff
+      }
+    }
+  }
+}