gwbeip/SpinalTemplateSbt
1
0
Fork 0
mirror of https://github.com/SpinalHDL/SpinalTemplateSbt.git synced 2025-10-22 23:58:44 +08:00
Code Issues Packages Projects Releases Wiki Activity

fix readme run-main into runMain

Browse Source
This commit is contained in:
Dolu1990
2019-01-03 20:04:08 +01:00
parent 0c8143eebc
commit 31f3b617a9
1 changed files with 3 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
README.md
View File

@@ -58,13 +58,13 @@ Open a terminal in the root of it and run "sbt run". At the first execution, the
cd SpinalTemplateSbt cd SpinalTemplateSbt
//If you want to generate the Verilog of your design //If you want to generate the Verilog of your design
sbt "run-main mylib.MyTopLevelVerilog" sbt "runMain mylib.MyTopLevelVerilog"
//If you want to generate the VHDL of your design //If you want to generate the VHDL of your design
sbt "run-main mylib.MyTopLevelVhdl" sbt "runMain mylib.MyTopLevelVhdl"
//If you want to run the scala written testbench //If you want to run the scala written testbench
sbt "run-main mylib.MyTopLevelSim" sbt "runMain mylib.MyTopLevelSim"
``` ```
The top level spinal code is defined into src\main\scala\mylib The top level spinal code is defined into src\main\scala\mylib