diff --git a/build.sbt b/build.sbt
index a7deee4..0494504 100644
--- a/build.sbt
+++ b/build.sbt
@@ -2,7 +2,7 @@ ThisBuild / version := "1.0"
 ThisBuild / scalaVersion := "2.11.12"
 ThisBuild / organization := "org.example"
 
-val spinalVersion = "1.5.0"
+val spinalVersion = "1.6.0"
 val spinalCore = "com.github.spinalhdl" %% "spinalhdl-core" % spinalVersion
 val spinalLib = "com.github.spinalhdl" %% "spinalhdl-lib" % spinalVersion
 val spinalIdslPlugin = compilerPlugin("com.github.spinalhdl" %% "spinalhdl-idsl-plugin" % spinalVersion)
diff --git a/build.sc b/build.sc
index b473abc..7750201 100644
--- a/build.sc
+++ b/build.sc
@@ -1,6 +1,6 @@
 import mill._, scalalib._
 
-val spinalVersion = "1.5.0"
+val spinalVersion = "1.6.0"
 
 object mylib extends SbtModule {
   def scalaVersion = "2.12.14"
diff --git a/src/main/scala/mylib/MyTopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala
index 196d09a..363884f 100644
--- a/src/main/scala/mylib/MyTopLevel.scala
+++ b/src/main/scala/mylib/MyTopLevel.scala
@@ -26,9 +26,9 @@ import scala.util.Random
 //Hardware definition
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in  Bool
-    val cond1 = in  Bool
-    val flag  = out Bool
+    val cond0 = in  Bool()
+    val cond1 = in  Bool()
+    val flag  = out Bool()
     val state = out UInt(8 bits)
   }
   val counter = Reg(UInt(8 bits)) init(0)