From 121ba1514dfa50ef87b76b3f70beb50494f5be8c Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 28 Nov 2022 10:49:19 +0100 Subject: [PATCH] Update README.md --- README.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 071a4bf..dd3cc1a 100644 --- a/README.md +++ b/README.md @@ -37,7 +37,7 @@ unsetenv VERILATOR_ROOT # For csh; ignore error if on bash unset VERILATOR_ROOT # For bash cd verilator git pull # Make sure we're up-to-date -git checkout v4.040 +git checkout v4.216 autoconf # Create ./configure script ./configure make -j$(nproc) @@ -59,13 +59,13 @@ Open a terminal in the root of it and run "sbt run". At the first execution, the cd SpinalTemplateSbt //If you want to generate the Verilog of your design -sbt "runMain mylib.MyTopLevelVerilog" +sbt "runMain projectname.MyTopLevelVerilog" //If you want to generate the VHDL of your design -sbt "runMain mylib.MyTopLevelVhdl" +sbt "runMain projectname.MyTopLevelVhdl" //If you want to run the scala written testbench -sbt "runMain mylib.MyTopLevelSim" +sbt "runMain projectname.MyTopLevelSim" ``` The top level spinal code is defined into src\main\scala\mylib @@ -128,13 +128,13 @@ Open a terminal in the root of it and execute your favorite mill command. At the cd SpinalTemplateSbt //If you want to generate the Verilog of your design -mill mylib.runMain mylib.MyTopLevelVerilog +mill projectname.runMain projectname.MyTopLevelVerilog //If you want to generate the VHDL of your design -mill mylib.runMain mylib.MyTopLevelVhdl +mill projectname.runMain projectname.MyTopLevelVhdl //If you want to run the scala written testbench -mill mylib.runMain mylib.MyTopLevelSim +mill projectname.runMain projectname.MyTopLevelSim ``` The top level spinal code is defined into src\main\scala\mylib