diff --git a/src/main/scala/mylib/MyTopLevel.scala b/src/main/scala/mylib/MyTopLevel.scala
index 19a8f22..a1c3a71 100644
--- a/src/main/scala/mylib/MyTopLevel.scala
+++ b/src/main/scala/mylib/MyTopLevel.scala
@@ -5,10 +5,10 @@ import spinal.core._
 // Hardware definition
 class MyTopLevel extends Component {
   val io = new Bundle {
-    val cond0 = in Bool ()
-    val cond1 = in Bool ()
-    val flag = out Bool ()
-    val state = out UInt (8 bits)
+    val cond0 = in  Bool()
+    val cond1 = in  Bool()
+    val flag  = out Bool()
+    val state = out UInt(8 bits)
   }
 
   val counter = Reg(UInt(8 bits)) init 0